STCSELR

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Interpret as STCSELR

SCLKSEL=others, SCLKDIV=others

STCA Clock Select Register

SCLKDIV	PCLKA Clock Frequency Division 0 (others): Settings other than above are prohibited. 1 (001): 1 2 (010): 1/2 3 (011): 1/3 4 (100): 1/4 5 (101): 1/5 6 (110): 1/6
SCLKSEL	STCA Clock Select 0 (000): PCLKA clock divided by 1 to 6 0 (others): Settings other than above are prohibited. 2 (010): Input clock from the REF50CK0 pin

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